Circuit arrangement and method for measuring current in vehicle braking systems

ABSTRACT

The present invention relates to a circuit arrangement for controlling the current in loads by modulation of the pulse width, comprising at least two driver stages ( 10 ) provided for the actuation of the loads, and one or more current measuring devices ( 3 ), and at least one multiplexer ( 4 ) conducting current measurement signals by way of the load current in the driver stages to one or more current measuring devices in dependence on one or more control signals ( 30, 31 ) for the multiplexer, said control signals being produced by a checking device ( 5 ). The invention further describes a method wherein the moment of the current measurements is controlled by an organized chronological order.

The present invention relates to a circuit arrangement according to thepreamble of claim 1, a method according to the preamble of claim 6, andthe use of the circuit arrangement of the invention in brake force ordriving dynamics controllers for automotive vehicles.

Electronic control units for automotive vehicle braking systems at anincreasing rate perform functions that either contribute to drivingsafety or recently even comprise basic vehicle functions such as thebraking function as such. Examples for functions for improving drivingsafety are anti-lock control (ABS) or driving dynamics control (ESP:Electronic Stability Program). In novel electronic braking systems likethe Electrohydraulic Brake (EHB) or the Electro-mechanic Brake (EMB) theelectronic control unit of the brake also performs the braking functionas such.

Still higher demands are therefore placed on reliability, failuretolerance and failure treatment of the electronic control units.

It is known in prior art to arrange for safety devices in electroniccontrol units for automotive vehicle braking systems that permitdetecting any occurring defects in the electronic componentsincorporated therein. Upon detection of a defect of this type,appropriate countermeasures such as disconnection of the control unit orchange-over of the control unit to an emergency mode may be taken.Safety-relevant circuit components may have a double or multiple(redundant) design for detecting defects. By comparing the function ofthe multiply provided circuit components, it is possible to detectfailure in many cases.

Semiconductor components such as power field effect transistors(Power-MOSFETs, FETs), among others for actuating the electro-mechanichydraulic valves that are provided to control the braking pressure areemployed in electronic controllers. In this arrangement, the hydraulicpressure can be controlled using a pulse-width modulated driver stagethat comprises at least one of the above-mentioned semiconductorcomponents (PWM-control).

In a pulse-width modulated control of a current that utilizes a digitalcontroller it is necessary to measure the current at determined momentsby way of an analog/digital converter ((A/D converter). If it is desiredto operate several pulse-width modulated drivers of this type at thesame time, one A/D converter per pulse-width-modulated stage is arrangedfor. This procedure is e.g. disadvantageous because it is difficult torealize, entailing high costs especially in large-scale production, andbecause an A/D converter is required for a short time only, mostly onlyfor a fraction of the time available. With duration of an A/D conversionof 5 μs and a frequency of pulse width modulation of 4 kHz, for example,the A/D converter would only be used to capacity of 2%.

An object of the present invention is to overcome these drawbacks.

The invention discloses the circuit arrangement according to claim 1.

According to the invention, the current values of severalpulse-width-modulated driver stages are preferably measured by means ofa number of current measuring devices for the individual control of theload current that is reduced compared to the number of thepulse-width-modulated driver stages.

The driver stages preferably provided to actuate inductive loads such ascoils may comprise one or more semiconductor switching elements such asfield effect transistors (FETs), sense-FETs, etc. The loads are valvecoils of electromagnetic actuating valves for hydraulic braking systemsin a particularly preferred feature.

It is preferred that the current measuring device is essentially an A/Dconverter. Most favorably one single A/D converter is employed forseveral pulse-width-modulated stages.

It is possible that the A/D converter also processes further channelsbeing converted, if these are not critical in terms of time. It hasshown that the sequence and/or the moment of the current measurement forthe individual pulse-width-modulated stages must be organized by thecircuit arrangement of the invention. It must be ensured in this respectthat no current measurement is omitted what could lead to an unstablecontrol, and that inaccuracies that could be caused by the organizationwill lead to errors of measurement in the current measurement to asmallest possible extent only.

The mode of function of a sense-FET that can preferably be implementedin the driver stage is e.g. disclosed in U.S. Pat. No. 5,079,456 orGerman patent application DE 195 20 735 A1. Accordingly, the loadcurrent of a power FET can be sensed because a similar FET whose surfaceis smaller is connected in parallel in close adjacency to the power FETon the semiconductor material. The current flowing through the smallerFET is largely proportional to the load current of the power FET,however, said current is smaller than the load current by a structurallydetermined numerical ratio that basically corresponds to the ratio ofconsumed chip surface between the power-FET and sense-FET.

A checking device is provided in the circuit arrangement for theorganization of the current measurements. Said checking device controlsthe allocation of the input of the A/D converter to the currentmeasuring devices of the driver stages, when requested.

The circuit arrangement of the invention preferably represents aconstruction unit, in particular a semiconductor chip, on which thecurrent measuring device, the device for reducing the measuringchannels, the final stages, and the A/D converter are grouped.

The present invention also relates to a method according to claim 6.

The moment of the current measurements is controlled by an organizedchronological order according to the invention.

In a first preferred embodiment, the organization is favorably effectedsuch that an exclusive highest priority is allocated alternatingly toeach driver stage in a predetermined chronological order.

Processing the request is carried out depending on the situation, inparticular according to the following steps:

-   A) First the A/D converter always processes the request of the    driver stage with the instantaneously highest priority.-   B) After step A) is terminated, a check is made whether further    unprocessed requests are prevailing in a memory (e.g. a queue).-   C) When the result of the check in step B) is positive, one of the    stored requests is processed.-   D) When the result of the check in step B) is negative, a request    for A/D conversion can be executed, if necessary, which does not    originate from a driver stage.

According to the first preferred embodiment, the memory is organized asa queue so that a request that is received earlier is always processedbefore a request that is received later (first-come-first-serve).

According to a second preferred embodiment for the organization of thecurrent measurements, the memory content is executed in chronologicalorder taking into consideration how much time is left for processing anindividual request. Among others, this feature takes the fact intoaccount that normally the possible time of measurement is limited due toa finite length of the actuating pulses. Consequently, processing storedrequests according to this embodiment takes place in an order thatconsiders the point of time of the edge of the actuating pulses. To thisend, especially the requests of driver stages are sorted in thechronological order of their values for the current duty cycle (dc) andprocessed in this order. It is especially favorable that sorting iscarried out in a chronological order, according to which the requestwith the smallest value for the duty cycle is always executed as first.Organizing the current measurements according to the embodimentdescribed herein will favorably obviate the need for the step indicatedhereinabove, according to which highest priority is always given to thestage with the current time slice.

As indicated already, a request for A/D conversion may be processedwhich does not originate from the driver stages if the memory is emptyand there is still sufficient time within the instantaneous time slice.Further, it may be expedient that the remaining time is used to executethe A/D channels in a predetermined order.

The circuit arrangement of the invention may be used in an especiallyadvantageous manner in electronic control units for automotive vehiclebraking and control systems, in particular in so-called integrated brakesystems, wherein the electronic control unit (ECU) is grouped with ahydraulic control unit (valve block, HCU) to form a monolithic block.

The demands placed on a current measuring device for measuring thecurrent on several pulse-width-modulated driver stages will be describedin detail in the following.

Further preferred embodiments of the invention become apparent from thesub claims and the subsequent description of Figures containing anembodiment for the invention.

In the accompanying drawings,

FIG. 1 shows the signal variation for a pulse-width modulated control inthe transient condition.

FIG. 2 shows diagrams for current measuring devices for the currentmeasurement in a low-side driver.

FIG. 3 is a circuit arrangement of the invention comprising an A/Dconverter, stages actuated by pulse-width modulation, and additional A/Dconverter channels.

FIG. 4 shows a diagram with different signal variations in the circuitarrangement according to FIG. 3.

The mode of function of the circuit arrangement of the invention in FIG.3 is initially described with reference to FIG. 1. The current I(partial image b), reference numeral 26, in an inductive load, e.g. coilof a valve or a motor, is adjusted by means of pulse-width-modulatedactuation of a FET 7 (FIG. 2). The current in the load is regulated bycurrent feedback. Partial image a) represents the course of an actuatingsignal 14 for a driver stage. The actuating pulse 37 has a square shape.The duration of a period of actuation T_(PWM) which is equal in alldriver stages (joint period), is composed of the time t_(ON) (referencenumeral 1) and t_(OFF) so that T_(PWM)=t_(ON)+t_(OFF) applies. The dutycycle is defined as dc=t_(ON)/T_(PWM). The load is actuated duringt_(ON), the actuating transistor is in a non-conductive state duringt_(OFF), and a re-circulation current flows via a current path providedfor this purpose and formed by a diode or an active circuit. With agiven value of dc, t_(ON)=dc*T_(PWM) results for the on-time of thecontrol transistor. The re-circulation time is calculated according tot_(OFF)=(1−dc)*T_(PWM). The course of the curves is illustrated in anideal fashion in FIG. 1. The current through the coil is approximatelylinear when the time constant τ of the coil is long compared to theperiod T_(PWM). Partial image b) shows that the coil current should bemeasured at a moment before the edge 37 of the actuating pulse 37. Themean value of the coil current can be determined in an especiallyfavorable manner when current measurement takes place as precisely aspossible at time t_(ON)/2.

FIG. 2 shows an example of a driver stage for actuating an inductiveload. Actuation of the load may occur by way of a low-side driver or ahigh-side driver (not shown). A measuring resistor 2 is arranged in themain path of the Main-FET 7 in partial image a), from which resistor 2the current-proportional voltage U_(S) can be tapped at terminals 8 and9. In partial image b) the current is used for current measurement byway of a separate current path of a sense-FET 7′.

Appropriately, the coil current is measured with the driver switched on,meaning during the time t_(ON), in particular at a moment that lies asexactly as possible in proximity to half the on-time t_(ON)/2. Thisarrangement is advantageous because the current value determined at thispoint of time corresponds in approximation to the mean value 25 of thecoil current. Alternatively it is possible to determine the coil currentalso during the re-circulation time t_(OFF) by way of a re-circulationdriver, e.g. roughly at the moment t_(OFF)/2.

FIG. 3 explains an example for a circuit arrangement of the invention,according to which exactly one A/D converter is used for currentmeasurement. Said arrangement comprises several driver stages 10actuated in pulse-width modulation as well as a defined number ofadditional A/D converter channels 35 and 35′ and an A/D converter 3 witha preceding analog multiplexer 4. Actuating logic 5 is connected to thedriver stages 10 and receives from them request signals by way of signallines 12. Logic 5 controls the A/D converter by way of line 31. Line 30is used to control the multiplexer 4. Analog signals are sent to the A/Dconverter by way of input 19. The digital output of A/D converter 33leads to memory locations 32 and 32′ storing the determined currentvalues or converted values of channels 35, 35′ (Ch1, Ch2). In addition,logic 5 includes a write line 34 allowing the control of the access ofdigital output 33 of the A/D converter to the current memory locations32, 32′ (de-multiplexer). From memory locations 32 with current valuesof the driver stages, data lines 36 extend to the driver stages 10 andtransmit digitized current signals.

It is preferred to subdivide the period T_(PWM) into time slices 11 ofequal length (see FIG. 4), and one of the time slices produced isassociated with each driver stage 10. The number of the driver stages isdesignated by k. In this case, t_(time-slot)=(1/k)*T_(PWM) applies tothe width of a time slice t_(time-slot). This solves the problem thatwith a simultaneous start of all actuating pulses in a short duty cycledc, the time span t_(ON) available for the current measurement would betoo short to execute all current measurements within the time available.

Each driver stage is enabled at the commencement of its time slice sothat the driver stages are not enabled at the same time. However, thisdoes not exclude a driver stage from being enabled longer than thecorresponding time slice, e.g. in such a way that the actuating signalof the driver is always modulated 100%. Current measurement by means ofthe A/D converter will occur when a driver stage sends a request signal(request) to the A/D converter by way of signal line 12 associated withsaid driver stage, said A/D converter executing the A/D conversion uponreceipt of a request signal either instantaneously or at a later pointof time.

Logic 5 acts such in processing the request signals that the driverstage has highest priority at a time lying within the time sliceassociated with it, meaning it is processed as first. FIG. 4 shows sixtime slices 11 for the driver stages Nos. 1 to 6. Associated with eachdriver stage is one of signals P1 to P6, with the respective signalbeing set to ‘high’ exclusively in the period of an associated priority.It may be expedient especially for processing signals with a short dutycycle to immediately interrupt (Interrupt) a request (e.g. a current A/Dconversion) as in the case explained above. It is, however, alsopossible to omit the processing of signals with a particularly shortduty cycle, to initially complete the present measurement and processimmediately thereafter the measurement of the driver stage with theinstantaneous priority.

Upon expiry of the time slice of a driver stage, the corresponding stagewill lose its priority. If a driver stage having no prioritynevertheless produces a request signal, the request to the A/D converterrelated to the request signal is input into a queue (Queue) by achecking device 5. This queue is processed when the driver stage havinginstantaneously highest priority either has terminated its currentmeasurement, or no current measurement is necessary. In processing thequeue, the request received as first is processed as first(First-Come-First-Serve). When the queue has been finished because thecurrent measurement requests have been processed, the A/D converter maybe utilized for measuring other signals. Thus, for example, a continuousmode may be provided in which the other signal channels 35, 35′ that arenot allocated to PWM stages are processed in a fixed order.

The above-described concept for current measurement and current controlhas a bottom limit (t_(on-min)) with respect to its shorter adjustableduty cycle (dc). When dc is smaller than t_(on-min), the time availableis no longer sufficient for current measurement. According to theinvention, it is therefore preferred to lower the bottom limit for theduty cycle in that at least with small values of dc, current measurementis performed by one memory element per stage so that the current valueof the stage is available for the A/D conversion also for a longerperiod of time. A memory element may be realized in a particularlysimple manner by a capacitor that maintains the voltage applied to theoutput at the moment of disabling of the driver stage.

Referring to FIG. 4 two critical cases during the operation of thecircuit arrangement in FIG. 3 are explained in detail. Time interval 27(T_(PWM)) is subdivided into six time intervals 11.

Extreme Case 1

End stage No. 4 is activated by signal pulse 13 (VDRVEN4) with a verysmall value of dc (roughly 5%) that simultaneously represents a bottomlimit value for the circuit of the example. The width of the signalpulse is referred to by t_(on-min). The testing time of the A/Dconverter or the sample time thereof must now be chosen such that atleast one A/D conversion or the sampling of the current value isterminated within the time t_(on-min). Otherwise, instability of thecontrol may be caused. The testing time of the A/D converter may beassessed in the way described hereinbelow.

Extreme Case 2

The second case deals with the maximum possible number of requestsproduced at the same time. As will be shown in the following, with sixtime slices maximally three requests without priority and one requestwith priority are possible. Simultaneous requests without priority areobtained when driver stage No. 1 is activated with a 100% dc for theduration t_(ON)=T_(PWM), meaning for the maximum possible time, driverstage No. 2 is activated with a dc of 2/3*100% and driver stage No. 3with a dc of 1/3*100%. A request with priority will now produce thesignal 13 in the time slice 4 which has been described alreadyhereinabove with respect to the extreme case 1. For the sake of clarity,only the actuating signals of stages Nos. 3 and 4 but not the signals ofstages Nos. 1 and 2 are plotted in FIG. 4. Thus, reference numerals 18and 13 designate the actuating signals of the third and fourth stage(VDRVEN 3 and 4). In the bottom part of FIG. 4 the current variations ofthe driver stages Nos. 3 and 4 are qualitatively illustrated in addition(13 and 14). The pulse commencement of the actuating signal 13 as wellas the pulse commencement of the actuating signals No. 1 (point of timeof start is optional), No. 2, and No. 3 is chosen such that t_(on)/2will lie at moment 16. At moment 16, a current measurement request(arrow 15) is produced e.g. by stage No. 1, yet this stage has alreadylost its priority. Another request is produced in the event of a requestby stage No. 4 which has the priority. Thus, there are four requeststhat are meant to be processed by the A/D converter in the order 28.After processing of driver stage No. 4 (VO4) has terminated, the queueis filled with a maximum of three (other) requests (VO1, VO2, VO3).Therefore, it is necessary to rate the parameters of the circuitarrangement in such a manner that the requests being processed can stillbe processed within the full time slice No. 4 because then the driverstage No. 3 is disabled.

When a total number of six drivers is made the basis, there will bemaximally four synchronous requests for driver stages in the extremecase when all driver stages are activated, as mentioned already. Thisdoes not exclude that also the stages Nos. 5 and 6 that are likewiseactivated under certain circumstances can produce further requestsignals. It follows, however, from logical considerations that theserequests cannot be placed at moment 16, where the requests of stagesNos. 1 to 4 may coincide, and for this reason usually have already beenprocessed or will still be produced at moment 16.

Estimation of the Time Required for Current Measurement

To calculate the time needed for a measurement operation, the timerequirement of the A/D converter (t_(conv)) must generally beconsidered, but also the transient effect of the measuring circuit isincluded in the reading time required which is designated by t_(sample)(reference numeral 17 in FIG. 4) in the following. To reduce the timerequired by the A/D converter, it is especially suitable to use a typeof A/D converters that initially read in a test value and thenintermediately store it (sample and hold, pipelining) so that asubsequent value is read in already at the input, while the presentvalue is still in the process of conversion. The clocked sampling(polling) of the A/D converter input 19, represented by arrows 23,causes another time delay or insecurity. Due to the clocked operation,the polling moments normally do not coincide with the moments of thecurrent measurement requests. The result is a time delay that isreferred to as t_(polling) in the following. The maximum deviation to beassumed is produced when a current measurement request occursimmediately after a polling operation so that t_(polling) can adopt thevalue t_(conv) as maximum. Therefore,T_(polling-max)=t_(conv) applies.

The maximum waiting time between the request and sampling of theprioritized stage (extreme case 1, see reference numeral 21) isdesignated by t_(wait-prio-max)) and calculated according tot _(wait-prio-max) =t _(polling-max) +t _(sample)=2*t _(conv).

In order that the current of a driver stage is still measured in time,first it must be demanded that the action of sampling by the A/Dconverter is terminated still during the interval t_(on). Therefore, therelationt_(wait-prio-max)≦t_(on-min)must apply, where t_(on-min) is the smallest possible value for t_(on).

An example suitable for the calculation to be performed herein is theextreme case 1 explained hereinabove with short t_(on) (pulse 13, driverstage No. 4). Curve 20 depicts the current caused hereby in the load.The current request takes place directly after moment 16 at momentt_(ON)/2.

The second extreme case that has already been explained by way of theexample of driver stage No. 3 determines another limit condition for thetime requirement of the A/D converter. As explained already, a maximumpossible number of requests prevail in this case. The maximum waitingtime between a request and its processing by the A/D converter, which isdesignated by t_(wait-max) in the following, is marked by the doublearrow 22 in the Figure. Consequently t_(wait-max) is calculatedaccording tot _(wait-max) =t _(polling-max) +t _(sample)+3*t _(conv)=5*t _(conv).

In general, the relation ist _(wait-max) =t _(polling-max) +t _(sample) +└k/2┘*t _(conv).

As a second boundary conditiont_(wait-max)≦t_(time-slot) applies.

It is possible to reduce t_(wait-prio-max) by 1*t_(conv) by interruptinga current conversion (interrupt) described hereinabove. No variation oft_(wait-max) is caused thereby.

The ripple mark 29 (see FIG. 1) of the current in the transientcondition is determined by the coil's discharge during the t_(off) time.Thus, it depends on the time constant of the discharge (and hence on theL of the coil) as well as on the present duty cycle. The ripple permitsdetecting the rise in current during the t_(ON) time. It can becalculated herefrom by what rate the current changes duringt_(wait-prio) or t_(wait). The result is a standard of inaccuracy thatmust be tolerated as caused by the method of the invention.

1. A circuit arrangement for controlling electrical current in loads bypulse width modulation, comprising at least two driver stages (10)provided for actuation of the loads and one or more current measuringdevices (3), the number of current measuring devices (3) being smallerthan the number of the driver stages, wherein at least one multiplexer(4) is provided conducting current measurement signals by way of theload current in the driver stages to one or more of the currentmeasuring devices in dependence on one or more control signals (30, 31)for the multiplexer, wherein the control signals are produced by achecking device (5), wherein the checking device comprises ade-multiplexer output (34) which allocates the digital output (33) of anA/D converter to current memory locations (32, 32′).
 2. The circuitarrangement as claimed in claim 1, wherein the driver stages (10) sendrequest signals to the checking device (5) by way of request lines (12).3. The circuit arrangement as claimed in claim 1, wherein the checkingdevice comprises a memory storing request events initiated by requestsignals.
 4. A method for current measurement with one or more currentmeasuring devices (3), and two or more driver stages (10), wherein thecurrents flowing in the driver stages are measured in each driver stageand the driver stages are actuated by means of individual controlsignals (14) for pulse width modulation of the load current flowing inthe driver stage, wherein the moment of the current measurements iscontrolled by an organized chronological order, and wherein the controlsignals of the driver stages have one joint period (27), said periodbeing subdivided into several time slices (11) and each time slice beingassociated with exactly one driver stage (10).
 5. The method as claimedin claim 4, wherein current measuring requests (15, 24) associated withthe driver stages are produced, and current measurement takes piece inresponse to a request.
 6. The method as claimed in claim 4, wherein adriver stage is enabled only within a time slice associated with it (13,18), especially at the beginning of said time slice.
 7. The method asclaimed in claim 4, wherein the organized allocation memorizes currentmeasurement requests intended for individual driver stages, andprocesses the current measurements on account of current measurementrequests according to a fixed order or an order determined by sorting.8. The method as claimed in claim 7, wherein a current measurementrequest of a driver stags is processed as first within the time sliceassociated with the driver stage.
 9. The method as claimed in claim 8,wherein a current measurement request of a driver stage, which is notallocated to the time slice that is instantaneously passed, is processedonly when former current measurement requests of driver stages that donot belong to the time slice have already been processed.
 10. Thecircuit arrangement as claimed in claim 8, wherein a current measurementrequest of a driver stage outside the time slice associated with thedriver stage that cannot be processed immediately is stored in a memory,and processing of the memorized requests is executed in a chronologicalorder that takes into consideration the moment of the edge (37) of theactuating pulses.